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NM24C09 - 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM

Download the NM24C09 datasheet PDF. This datasheet also covers the NM24C08 variant, as both devices belong to the same 8k-bit standard 2-wire bus interface serial eeprom family and are provided as variant models within a single manufacturer datasheet.

General Description

The NM24C08/09 devices are 8192 bits of CMOS non-volatile electrically erasable memory.

These devices conform to all specifications in the Standard IIC 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (NM24C08_FairchildSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
NM24C09 8K-Bit Serial EEPROM National
NM24C02 2K-Bit Standard 2-Wire Bus Fairchild
NM24C03 Serial EEPROM National Semiconductor
NM24C03 2K-Bit Standard 2-Wire Bus Fairchild
NM24C04 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM Fairchild

Other Datasheets by Fairchild (now onsemi)

Part Number Description
NM24C16U (NM24C16U / NM24C17U) 16K-Bit Serial EEPROM
NM24C17U (NM24C16U / NM24C17U) 16K-Bit Serial EEPROM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
NM24C08/09 – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM NM24C08/09 – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM February 2000 General Description The NM24C08/09 devices are 8192 bits of CMOS non-volatile electrically erasable memory. These devices conform to all specifications in the Standard IIC 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements. The upper half (upper 4Kbit) of the memory of the NM24C09 can be write protected by connecting the WP pin to VCC. This section of memory then becomes unalterable unless WP is switched to VSS. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s).